1. Field of the Invention
The present invention relates to a power applying circuit, and more particularly, to an improved power applying circuit capable of clearing an undesired information stored in a memory device of an internal logic circuit.
2. Description of the Related Art
Generally, when power is applied to a product, an unnecessary arbitrary information is stored in the memory devices disposed in an internal logic circuit under each initial condition. Since the initial condition of the product cannot easily be cleared by changing a design or process, an erroneous operation is carried out for a time and then enters a stable operating condition.
Conventionally, when power is applied to a product, a detecting circuit is used to detect the applied power. In the detecting circuit, a capacitor and a resistor are employed. The capacitor and resistor are formed by diffusion. Such a diffusion process has a normal deviation of 10 to 20%. Therefore, to reduce the deviation in the process, a method of designing a large resistor has been adopted. However, the resistor designed in such a method occupies a large chip area.
In case of a gate array among application specific integrated circuit (ASIC) products, a capacitor or a resistor cannot be formed in an array. That is, according to the gate array, after wafers having logic element gates are fabricated in advance, a three-stage mask step is performed for a metal wiring to complete a fabrication process, but the capacitor or resistor cannot be arranged by a metal process. In addition, a power applying circuit which detects a power activation is maintained in a non-active condition after power is applied thereto. Consequently, an unnecessary initial information of the memory device in the internal logic circuit cannot be cleared or reset, which is disadvantageous in conventional power applying circuits.